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advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 1 of 14 pbl 387 72/1 subscriber line interface circuit key features ? on-chip high voltage ring generation - balanced, up to 80 v peak - any ring waveform - 5 ren ringing load - short circuit safe - automatic gain control of ringing signal ? low on-hook power consumption in active state (65mw @ v bat =-80v) ? automatic switching between ringing battery (v bat ) and talk battery (v tbat ) ? only +5v and battery supplies needed ? pulse metering and on-hook transmission ? ul-1950 and mtu compliant on-hook line voltage ? programmable ring trip threshold ? 3.3v compatible logic interface ? silent or fast polarity reversal ? 28-pin soic package applications ? cable modems ? voice over dsl (vodsl) ? terminal adapters ? isdn terminal adapters (nt1+) ? voice over ip (voip) ? routers ? integrated access devices (iad) ? other short loop applications description the pbl 387 72/1 subscriber line interface circuit (slic) is a 90 v bipolar integrated circuit with on-chip high voltage ring generation for use in short loop applications. the pbl 387 72/1 slic has been optimized for low power consumption, low total line interface cost and for a high degree of flexibility meeting worldwide requirements. the pbl 387 72/1 slic supplies a balanced ringing signal of any waveform (e.g. sinewave, trapezoidal, etc.) figure 1. block diagram up to 80 v peak (85 v dc supply) to the subscriber line across a load of up to 5ren the pbl 387 72/1 supplies programmable constant current to the subscriber loop, sourced from the talk battery. the on- hook line voltage of 43 v to 56 v is derived from the ring battery. all battery switching is internal to the device and is automatic. to further reduce power consumption the automatic gain control for the ring signal (agcr) keeps the level always adjusted to the maximum, that can be sourced from the available dc ringing battery. the slic incorporates loop current, ground key and ring trip detection functions. the pbl 387 72/1 is compatible with loop start signaling. two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the slic in conjunction with any standard codec. the line terminating impedance and balance impedance is programmable (via hardware or software) and may be complex or real for worldwide compliance. tip and ring voltages are ul-1950 compliant, i.e. no two- wire line voltage exceeds 56 v. the pbl 387 72/1 slic is available in a surface mount 28 soic package. ref spr cring ring trip detector input decoder and control off-hook detector vf signal transmission two-wire interface vtbat c1 c2 c3 det plc lp pld vtx rsn tipx hp ringx bgnd line feed controller and longitudinal signal suppression ringing control vr vbat agnd vcc prt vtb 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 2 of 14 maximum ratings parameter symbol min max unit temperature, humidity storage temperature range t stg -55 +150 c operating temperature range t amb -40 +110 c operating junction temperature range, note 1 t j -40 +140 c power supply, -40c t amb +85c v cc with respect to agnd v cc -0.4 6.5 v v tbat with respect to a/bgnd v tbat v bat 0.4 v v bat with respect to bgnd, continuous v bat -85 0.4 v power dissipation continuous power dissipation at t amb +85 c p d tbd w ground voltage between agnd and bgnd v g -5 v cc v digital inputs, outputs (c1, c2, c3, det) input voltage v id -0.4 v cc v output voltage (det not active) v od -0.4 v cc v output current (det) i od 30 ma tipx and ringx terminals, -40c < t amb < +85c, v bat = -80 v tipx or ringx current i tipx , i ringx -100 +100 ma tipx or ringx voltage, continuous (referenced to agnd) v ta , v ra v bat 2v tipx or ringx, pulse < 10 ms, t rep > 10 s, note 2 v ta , v ra v bat -5 5 v tipx or ringx, pulse < 1 s, t rep > 10 s, note 2 v ta , v ra v bat -25 10 v tip or ring, pulse < 250 ns, t rep > 10 s, note 2 v ta , v ra v bat -35 15 v recommended operating condition parameter symbol min max unit ambient temperature t amb -40 +85 c v cc with respect to agnd v cc 4.75 5.25 v v tbat with respect to bgnd v tbat v bat -10 v v bat with respect to bgnd v bat -80 -10 v notes, maximum ratings 1. the circuit includes thermal protection. operation above maximum junction temperature may degrade device reliability. 2. with the diodes d b and d tb included, see figure 8. 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 3 of 14 electrical characteristics -40 c t amb +85 c, v cc = +5 v 5 %, v tbat = -32 v to ?10 v, v bat = -80 v, r lc = 18.7 k ? , (i l = 27 ma), z l = 600 ? , r ld = 50 k ? , r f1 = r f2 = 0 ? , r ref = 15.0 k ? , c hp = 33 nf, c lp = 0.47 f, r t = 120 k ? , r rx = 120 k ? . current definition: current is positive if flowing into a pin unless stated otherwise. ?active state? includes ?active, reverse polarity state? unless otherwise specified. ref parameter fig conditions min typ max unit two-wire port overload level, v tro 2 active state off-hook, i ldc 10 ma 1% thd, note 1 1.0 v peak on-hook, i ldc 5 ma 1.0 v peak metering, i ldc 10 ma z lm = 200 ? , f = 16 khz 0.7 v peak input impedance, z trx note 2 z t /200 longitudinal impedance, z lot , z lor 0 < f < 100 hz 20 35 ? /wire longitudinal current limit, i lot , i lor active state 28 ma rms /wire longitudinal to metallic balance, b lm 3 ieee standard 455-1985, r lt =r lr = 368 ? 0.2 khz < f < 1.0 khz 53 70 db 1.0 khz < f < 3.4 khz 53 70 db longitudinal to metallic balance, b lme 3r lt =r lr = 300 ? e lo 3 active state b lme = 20 ? log ???? 0.2 khz f 1.0 khz 53 70 db v tr 1.0 khz < f < 3.4 khz 53 70 db longitudinal to four-wire balance, b lfe 3 active state e lo b lfe = 20 ? log ???? 0.2 khz f 1.0 khz 59 70 db v tx 1.0 khz < f < 3.4 khz 59 70 db figure 2. overload level, v tro , two- wire port ? = << 600 , 1 l r l r c r t = 120 k ? , r rx = 120 k ? figure 3 . longitudinal to metallic, b lm , b lme and longitudinal to four- wire, b lfe balance ? = = ? << 300 , 150 1 lt r lr r c or 368 ? r t = 120 k ? , r rx = 120 k ? pbl 387 72 tipx ringx rsn vtx r t r rx e rx r l v tro i ldc c pbl 387 72 tipx ringx rsn vtx r t r rx v tx r lt c v tr r lr e lo 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 4 of 14 ref parameter fig conditions min typ max unit four-wire to longitudinal balance, b fle 4 active state e rx b fle = 20 ? log ???? 0.2 khz f 3.4 khz 40 58 db v lo two-wire return loss, r |z trx + z l | r = 20 ? log ????? 0.2 khz < f < 0.5 khz 25 db |z trx - z l | 0.5 khz < f < 1.0 khz 27 db 1.0 khz < f < 3.4 khz, note 3 23 db tipx idle voltage, v ti active normal, i l = 0 -1.0 v ringx idle voltage, v ri active normal, i l = 0 -44 -51 -56 v open loop voltage, |v tropen |active, i l = 0 43 55 v four-wire transmit port (output vtx) overload level, v txo 5 off-hook, i ldc 10ma load impedance > 20 k ? , 0.5 v peak on-hook, i ldc 5ma load impedance > 20 k ? ,0.5 v peak 1% thd, note 4 output offset voltage, ? v tx -60 0 60 mv output impedance, z tx 0.2 khz < f < 3.4 khz 5 20 ? output dc voltage, v txdc 0v four-wire receive port (rsn, receive summing node) rsn dc voltage, v rsndc i rsn = 0 ma -25 gnd +25 mv rsn impedance 0.2 khz < f < 3.4 khz 10 50 ? rsn current, i rsn , to metallic loop 0.3 khz < f < 3.4 khz 400 ratio current ,i l , gain, rsn figure 4. four-wire to longitudinal, b fle balance ? = = ? << 300 , 150 1 lt r lr r c r t = 120 k ? , r rx = 120 k ? figure 5. overload level, v txo , four-wire transmit port ? = << 600 , 1 l r l r c r t = 120 k ? , r rx = 120 k ? pbl 387 72 tipx ringx rsn vtx r t r rx e rx r lt c v tr r lr v lo pbl 387 72 tipx ringx rsn vtx r t r rx r l i ldc c e l v txo 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 5 of 14 ref parameter fig conditions min typ max unit frequency response two-wire to four-wire, g 2-4 6 relative to 0 dbm, 1.0 khz. e rx = 0 v 0.3 khz < f < 3.4 khz -0.15 0.15 db f = 8.0 khz, 12 khz, 16 khz -0.5 -0.1 0.1 db four-wire to two-wire, g 4-2 6 relative to 0 dbm, 1.0 khz. e l = 0 v 0.3 khz < f < 3.4 khz -0.15 0.15 db f = 8 khz, 12 khz, -1.0 -0.2 0 db f = 16 khz -1.0 -0.3 0 db four-wire to four-wire, g 4-4 relative to 0 dbm, 1.0 khz. e l = 0 v 0.3 khz < f < 3.4 khz -0.15 0.15 db insertion loss two-wire to four-wire, g 2-4 6 0 dbm, 1.0 khz, note 5 -6.22 -6.02 -5.82 db v tx g 2-4 = 20 ? log ???? , e rx = 0 v tr four-wire to two-wire, g 4-2 6 0 dbm, 1.0 khz, notes 5, 6 -0.2 0.2 db v tr g 4-2 = 20 ? log ???? , e l = 0 e rx gain tracking two-wire to four-wire 6 ref. -10 dbm, 1.0 khz, note 7 r ldc 2k ? -40 dbm to +3 dbm -0.1 0.1 db -55 dbm to -40 dbm -0.2 0.2 db four-wire to two-wire 6 ref. -10 dbm, 1.0 khz, note 7 r ldc 2k ? -40 dbm to +3 dbm -0.1 0.1 db -55 dbm to -40 dbm -0.2 0.2 db noise idle channel noise at two-wire port c-message weighting 5 12 dbrnc (tipx-ringx) psophometrical weighting -85 -78 dbmp note 8 harmonic distortion two-wire to four-wire 6 0 dbm, 1.0 khz test signal -50 db four-wire to two-wire 0.3 khz < f < 3.4 khz -50 db figure 6. frequency response, insertion loss, gain tracking. ? = << 600 , 1 l r l r c r t = 120 k ? , r rx = 120 k ? pbl 387 72 tipx ringx rsn vtx r t r rx e rx r l v tr i ldc c e l v t x 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 6 of 14 ref parameter fig conditions min typ max unit ring signal input, vr bias current, i vrdc +1 v < v rdc < -1 v, r vr = 200 k ? 0415na bias voltage, v vrdc r vr = 200 k ? 0v input impedance, ? z r ? 0 hz < f r < 100 hz, r vr = ? 20 m ? gain, vr to tipx-ringx, g r-2 z l = 8 k ? , f = 20 hz, v r = 0.6 v pk note 9 109 ratio battery feed characteristics constant loop current, i lconst r lc = 500 - 10.4 ? ln(32 ? 10 -3 ? i lprog ) i lprog i lprog 18 < i lprog < 30 ma 0.95 i lprog i lprog 1.05 i lprog ma loop current detector programmable threshold, i lth i lth = 500 , i lth > 10 ma 0.9?i lth i lth 1.1?i lth ma r ld ring trip detector programmable threshold, i lth i lth = 4000 , i lth > 10 ma 0.9?i lth i lth 1.1?i lth ma r rt ground key detector ground key detector threshold i ltipx and i lringx current difference to trigger ground key det. 11 15 19 ma digital inputs (c1, c2, c3) input low voltage, v il 00.5v input high voltage, v ih 2.5 v cc v input low current, |i il |v il = 0.5 200 a input high current, i ih v ih = 2.5 v 200 a detector output (det) output low voltage, v ol i ol = 1 ma 0.1 0.6 v internal pull-up resistor to v cc 10 k ? power dissipation (v tb = -24v, v bat =-80v) p 1 open circuit state 16 mw active state p 2 longitudinal current = 0 ma, i l = 0 ma 65 mw p 3 r l = 300 ? (off-hook) 0.50 w p 4 r l = 600 ? (off-hook) 0.29 w ringing state p 5 r l = 7k ? (ac load 1 bell), i ldc = 0 ma 0.36 w ringing: sine , 20 hz, max. amplitude power supply currents (v tb = -24v, v bat =-80v) v cc current, i cc open circuit state 1.4 ma v tbat current, i tbat open circuit state 0 ma v bat current, i bat open circuit state -0.07 ma v tb current, i tb open circuit state -0.13 ma v cc current, i cc active state, on-hook 2.4 ma v tbat current, i tbat active state, on-hook 0 ma v bat current, i bat active state, on-hook -0.6 ma v tb current, i tb active state, on-hook -0.2 ma v cc current, i cc ringing state, on-hook, no ring signal 7.1 ma v tbat current, i tbat ringing state, on-hook, no ring signal 0 ma v bat current, i bat ringing state, on-hook, no ring signal -2.7 ma v tb current, i tb ringing state, on-hook, no ring signal -1 ma 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 7 of 14 ref parameter fig conditions min typ max unit power supply rejection ratios v cc to 2- or 4-wire port active state f = 1 khz, v n = 100 mv tbd db v tbat to 2- or 4-wire port active state f = 1 khz, v n = 100 mv tbd db v bat to 2- or 4-wire port active state f = 1 khz, v n = 100 mv tbd db temperature guard junction threshold temperature, t jg 150 c thermal resistance junction to pins, ja , note 10 50 c/w junction to pins, jp 30 c/w notes, electrical characteristics 1. the overload level is automatically expanded to 3 v peak when the signal level is > 1.0 v peak and is specified at the two-wire port with the signal source at the four-wire receive port. 2. the two-wire impedance is programmable by selection of external component values according to: z trx = z t /(g 2-4s ? rsn ) where: z trx = impedance between the tipx and ringx terminals z t = programming network between the vtx and rsn terminals g 2-4s = transmit gain, nominally = 0.5 rsn = receive summing node current gain, nominally = 400. rsn is the ratio between the current flowing from ringx to tipx and the current flowing into the rsn pin (current is defined as positive flowing into the receive summing node, rsn and when flowing from ringx to tipx). 3. higher return loss values can be achieved by adding a reactive component to r t , the two-wire terminating impedance programming resistance, e.g. by dividing r t into two equal halves and connecting a capacitor from the common point to ground. 4. the overload level is automatically expanded as needed up to 1.5 v peak when the signal level >0.5 v peak and is specified at the four-wire transmit port, vtx, with the signal source at the two-wire port. note that the gain from the two-wire port to the four- wire transmit port is g 2-4s = 0.5. 5. secondary protection resistors r f1 and r f2 impact the insertion loss (refer to section functional description and application information). the specified insertion loss is for r f1 = r f2 = 0. 6. the specified insertion loss tolerance does not include errors caused by external components. 7. the level is specified at the four-wire receive port (e rx , figure 6) and referenced to a 600 ? impedance level. 8. the two-wire idle noise is specified with the four- wire receive port grounded (e rx = 0, figure 6). the four-wire idle noise at vtx is the two-wire value reduced by 6 db and is specified with the two-wire port terminated in 600 ? (r l ). the vtx noise specification is referenced to a 600 ? impedance level. 9. agcr, automatic gain control ringing, is not activated with a signal level as low as 0.6 v peak . 10. junction to ambient thermal resistance is dependent on pcb layout and many others factors external to the pbl 387 72/1 device. 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 8 of 14 figure 7 . pin configuration, 28 pin soic package, top view slic operating states state c3 c2 c1 slic operating state active detector (det response) 0000tipx and ringx open circuit no active detector (det is set high) 1001ringing ring trip detector (det active low) 2010active loop current detector (det active low) 3011active, test of line voltage loop voltage measurement (det pulse train) 4100not applicable 5101active, gro und key, ground fault test ground key detector and loop ground fault detector (det active high) 6110active, reverse polarity loop current detector (det active low) 7111active rev polarity, gro und fault test loop ground fault detector (det active high) table 1. slic operating states. 1 2 3 4 5 6 7 8 9 10 11 28 27 26 25 24 23 22 21 20 19 18 bw bw bw hp bgnd ringx tipx vtb c1 vtx rsn agnd vr c2 c3 pld lp vbat det vtbat vcc 12 17 spr plc 28-pin soic 16 ref 15 cring 13 bw 14 bw prt 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 9 of 14 pin description 28l soic symbol description 1bw b at w ing (note 1) 2bw b at w ing (note 1) 3bw b at w ing (note 1) 4hp h igh p ass ac/dc separation capacitor, c hp, connects between this pin and tipx. 5bgnd b attery g rou nd . shall be tied together with agnd. 6 ringx the tipx and ringx pins connect to the tip and ring leads of the two-wire interface via over voltage protection components (and optional test access switch). 7 tipx the tipx and ringx pins connect to the tip and ring leads of the two-wire interface via over voltage protection components (and optional test access switch). 8 vtbat t alk bat tery. the dc loop current is supplied to tipx and ringx from this battery voltage. negative with respect to bgnd. 9vbat ringing bat tery supply voltage. negative with respect to bgnd. 10 vtb internal slic bias voltage. connected to the talk battery supply. refer to the application diagram in figure 8. may be connected to any voltage between vtb and ?5 v. 11 lp l ow p ass saturation guard filter capacitor, c lp , connects between this pin and vbat to filter out noise and improve psrr. 12 spr s ilent p olarity r eversal. the polarity reversal time can be set with a capacitor connected between this pin and agnd. 13 bw b at w ing (note 1) 14 bw b at w ing (note 1) 15 cring c ring connects between this pin and agnd. required for the ring signal generation. 16 ref a 15 k ? resistor connected between this pin and agnd sets an internal slic reference current. the value must not be changed. 17 plc p rogrammable l ine c urrent. the constant current dc feed is programmed by a resistor, r lc , connected from this pin to agnd. 18 prt p rogrammable r ing t rip resistor, r rt , connected between this pin and agnd. sets the ring trip threshold. 19 pld p rogrammable l oop d etector threshold. the loop detection threshold is programmed by a resistor, r ld , connected between this pin and agnd. 20 vcc +5 v power supply. 21 c3 c1, c2, c3 are digital inputs, which c ontrol the slic operating 22 c2 states. refer to table 1, slic operating states. 23 c1 24 det det ector output. active low when indicating loop or ring trip detection, active high when indicating ground key detection. 25 vr low voltage r ing signal input. reference to ground. 26 agnd a nalog g rou nd , shall be tied together with bgnd. 27 rsn r eceive s umming n ode. 400 times the current flowing into this pin equals the metallic (transversal) current flowing from ringx to tipx. programming networks for two-wire impedance and receive gain connect to the receive summing node. 28 vtx t ransmit vf output. the ac voltage difference between tipx and ringx, the ac metallic voltage, is reproduced as an unbalanced gnd referenced signal at vtx with a gain of 0.5. the two-wire impedance-programming network connects between vtx and rsn. notes 1. a batwing is a package pin, which provides a low thermal resistance path to the silicon chip via the lead frame. by soldering the batwing pins to pcb copper foil the device can be efficiently cooled. note that batwing pins are at the same voltage as the vbat pin (substrate voltage). 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 10 of 14 functional description and applications information introduction the figure 8. diagram shows the pbl 387 72/1 in a typical application with a non-programmable, combo i, codec. the pbl 387 72/1 can equally well be used with software programmable codecs. the component values chosen for the application diagram example yield a two-wire impedance of 600 ? , resistive. the balance resistor is calculated for a line impedance, z l (compromise impedance), of 600 ? , resistive. the two-wire to four-wire gain is set by r tx and r fb to produce the digital mw level at the pcm transmit bus for a signal level of +3 dbm applied to the two-wire input (tip and ring). a received digital mw at the pcm receive bus results in a ?3 dbm signal level across the compromise impedance (600 ? ) connected at the two-wire port (tip and ring). the gain calculations are based on national semiconductor combo i codec, tp 3054. r f1 , r f2 and the clamp ?ovp? make up the overvoltage protection network. c tc and c rc clamp fast transients that may bypass the ovp clamp and also filter high frequency interference (rfi filter). c hp and c lp are coupling capacitors within two slic feedback loops that control slic battery feed and slic voice frequency transmission. c tb , c b , c vcc are power supply bypass capacitors. d tb is a diode that is part of the battery switching function. d b prevents reverse currents from the vb supply rail during application of negative over voltages. d bb is normally reverse biased, but conducts supply vtb to the vbat terminal in case the voltage vb would fail. r t sets the two-wire impedance (note that r t may be replaced with a complex impedance, z t , to implement complex terminating impedance). the ratio between r fb and r tx sets the transmit gain. r rx sets the receive gain. r ld sets the loop current detector threshold. r lc sets the constant dc loop current. r ref sets a slic reference current (must be 15.0 k ? , 1%, as specified). r rt sets the ring trip loop current detector threshold. c ring is used for the high voltage ringing signal agc (automatic gain control) function. v tb is the talk battery supply, i.e. the negative supply voltage that sources the loop current. v b is the ringing battery, i.e. the negative supply voltage that is used to power the slic, while ringing the line. 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 11 of 14 figure 8. single channel subscriber line interface with pbl 387 72/1 and combo i type codec. resistors: (values according to iec-63 e96 series) r ld = 49.9 k ? 1% 1/10 w r lc = 18.7 k ? 1% 1/10 w r rt = 69.8 k ? 1% 1/10 w r ref = 15.0 k ? 1% 1/10 w r rx = 232 k ? 1% 1/10 w r vr = 200 k ? 1% 1/10 w r tx = 28.0 k ? 1% 1/10 w r t = 104 k ? 1% 1/10 w r fb = 73.2 k ? 1% 1/10 w r b = 110 k ? 1% 1/10 w r f1 =r f2 =40 ? 1% match, line protection resistor. capacitors: (values according to iec-63 e6 series) c tb = 150nf 100 v 20% c b = 100nf 100 v 20% c vcc = 100nf 10 v 20% c tc = 1.0nf 100 v 20% c rc = 1.0nf 100 v 20% c hp = 33nf 100 v 20% c lp = 470nf 100 v 20% c gg = 220nf 100 v 20% c ring = 470nf 10 v 20% c vr = 0.33f 10 v 20% c spr = optional 10 v 20% diodes: d b = d tb = d bb =1n4448 ovp: secondary protection clamp (e g bourns/power innovations tisp pbl3, which serves two lines). the ground terminals of the secondary protection should be connected to the common ground on the printed board assembly with a track as short and wide as possible, preferably to a ground plane. c tb d b c lp d tb vtb vb c rc ovp vb r f1 r f2 c gg c tc pld prt plc ref pld vtb lp spr bw rsn agnd vr det hp bw bw hp hp hp hp bgnd bw vtx pbl38772 c2 ringx c1 c3 vcc tipx vtbat vbat r tx r rx tip ring c ring c b bw cring c hp vcc c vr vr c spr system control interface 0 - + 0 codec/ filter - + txpcmbus rxpcmbus dx dr r ld r rt r lc r ref r fb c vcc r t r b r vr d bb 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 12 of 14 figure 9 . battery feed characteristic a: i l (@v tr =0) = i lconst = i lprog lprog i lprog i lprog i lc r ) 3 10 32 ln( 4 . 10 500 ? ? ? ? ? = (note: i l in ma and r lc in k ? ) b,c: i l = i lconst , v tr (@c) = v app - r feed ? i lprog d: ? ? = 25 2 feed r e: i l 5.5ma , v tr = v app - r feed ? 5.5 ma f: v app (@i l =0) = v tb - v f * - 4.2v * v f forward voltage of diode d tb g: i l 5ma h: ? ? = 25 2 feed r j: ? v tropen ? 56 v limited by the slic @ i l = 0 ma (open loop voltage) if v bat less than 56 v the v bat v tropen v 6 . 4 ? = dc characteristics v tr [v] e f d c b a g h j 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 13 of 14 mechanical drawing 28 soic 4 .com u datasheet
advance information pbl 387 72/1 shortform rev. p5 feb. 14, 2001 14 of 14 information given in this data sheet is believed to be accurate and reliable. however no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of ericsson microelectronics ab. these products are sold only according to ericsson microelectronics general conditions of sale, unless otherwise confirmed in writing. specifications subject to change without notice. ? ericsson microelectronics ab, 2000 this product is an original ericsson product protected by us, european and other patents. ericsson microelectronics ab se-164 81 kista-stockholm, sweden telephone: +46 8 757 50 00 4 .com u datasheet

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